Microminiature field emitters are well known in the microelectronics art. These microminiature field emitters are finding widespread use as electron sources in microelectronic devices. For example, field emitters may be used as electron guns in flat panel displays for use in aviation, automobiles, workstations, laptops, head wearable displays, head-up displays, outdoor signage, or practically any application for a screen which conveys information through light emission. Field emitters may also be used in non-display applications such as power supplies, printers, and X-ray sensors.
When used in a display, the electrons emitted by a field emitter are directed to an cathodoluminescent material. These display devices are commonly called Field Emitter Displays (FEDs). A field emitter used in a display may include a microelectronic emission surface, also referred to as a "tip" or "microtip". Conical, pyramidal, curved and linear pointed tips are often used. Alternatively, a flat tip of low work function material may be provided. An emitting electrode typically electrically contacts the tip. An extraction electrode or "gate" may be provided adjacent, but not touching, the field emission tip, to form an electron emission gap therebetween. Upon application of an appropriate voltage between the emitting electrode and the gate, quantum mechanical tunneling, or other known phenomena, cause the tip to emit electrons. In microelectronic applications, an array of field emission tips may be formed on the horizontal face of a substrate such as a silicon semiconductor substrate, glass plate, or ceramic plate. Emitting electrodes, gates and other electrodes may be provided on or in the substrate as necessary. Support circuitry may also be fabricated on or in the substrate.
The FEDs may be constructed using various techniques and materials, which are only now being perfected. Preferred FED's may be constructed of semiconductor materials, such as silicon. There are two predominant processes for making field emitters; "well first" processes, and "tip first" processes. In well first processes, such as a Spindt process, wells are first formed in and/or on a substrate, and tips are later formed in the wells. In tip first processes, the tips are formed first, and the wells are formed around the tips. There are multitudes of variations of both the well first and the tip first processes. The present invention relates primarily to well first processes of making FEDs and FEDs made by a well first process.
The electrical theory underlying the operation of an FED is similar to that for a conventional CRT. Electrons supplied by a cathode are emitted from the tips in the direction of a display surface, for example. The emitted electrons strike phosphors on the inside of the display which excites the phosphors and causes them to luminesce. An image is produced by the collection of luminescing phosphors on the inside of the display screen. This process is a very efficient way of generating a lighted image.
In a CRT, a single electron gun is provided to generate all of the electrons which impinge on the display screen. A complicated aiming device, usually comprising high power consuming electromagnets, is required in a CRT to direct the electron stream towards the desired screen pixels. The combination of the electron gun and aiming device behind the screen necessarily make a CRT display prohibitively bulky.
FEDs, on the other hand, may be relatively thin. Each pixel of an FED has its own electron source, typically an array or grouping of emitting microtips. The voltage difference between the cathode and the gate causes electrons to be emitted from the microtips which are in electrical proximity with the cathode. The FEDs may be thin because the microtips, which are the equivalent of an electron gun in a CRT, are extremely small. Further, an FED does not require an aiming device, because each pixel has its own electron gun (i.e. an array of emitters) positioned directly behind it. The emitters need only be capable of emitting electrons in a direction generally normal to the FED substrate.
The operation of an FED may be improved by spacing the emitter microtips in a relatively densely packed array. Close spacing of the emitter tips permits the use of more emitter tips per pixel, and a corresponding increase of electron flux per pixel and/or a reduction in the power required from each individual emitter tip. This results in a brighter display and a display that is less susceptible to be adversely affected by the failure of some of the emitter tips or low yield of emitter tip formation.
The operation of an FED may also be improved by reducing the distance between the emitter microtips and the gate which surrounds them. Electron emission may be improved by striving to make the gate opening surrounding the emitter microtip on the same order of magnitude as the radius of the emitter microtip "tip" itself. By reducing the distance between the gate and the emitter tip, the turn-on power requirements of the gates may be reduced, thereby making the FED more energy efficient and less susceptible to gate to tip leakage. In order to produce such gates with small openings, it is necessary to make wells with correspondingly small openings.
The desired tight spacing and small openings of wells may be very difficult, if not impossible, to achieve using many of the previously known methods of well formation. For example, one known method of forming wells consisted of depositing a layer of photoresistive material over the substrate in which the wells are to be formed. A mask is then placed over the photoresistive material, and selective portions of the photoresistive material are exposed to light through openings in. the mask. The mask is then removed, and the exposed (or unexposed) portions of the photoresistive material are then removed. The remaining photoresistive material may be used to mask the substrate for subsequent deposition and/or etching steps. The wells may be formed by etching into the substrate between the remaining photoresistive material or by depositing material on the substrate. After the wells are formed, the remaining photoresistive material is removed. Using the foregoing method, the spacing and opening size of wells is limited by the fineness of the mask placed over the photoresistive material. Furthermore, the finer the mask, the more delicate it is and the harder it is to work with.
As an alternative to the use of a physical mask, laser interferometry may be employed to impart a finely spaced pattern on photoresistive material. For example, Hanawa et al. U.S. Pat. No. 5,328,560 (Jul. 12, 1994) for a Method Of Manufacturing Semiconductor Device, discloses the use of an excimer laser to selectively irradiate a negative type resist layer for the production of a semiconductor device. By selective irradiation, a protonic acid is generated in the exposed portion of the resist layer. The resist is than baked and developed resulting in the non-exposed portion of the resist layer being dissolved. A resist pattern is left which may be used to form features in or on an underlying semiconductor substrate.
Hanawa et al. also disclose the undesireablity of the effects of multiple reflection in the photoresist film produced by interference between irradiated light and light reflected from the underlying semiconductor substrate. In order to prevent the effects of multiple reflections in film, an organic antireflective film is utilized. The antireflective film is not disclosed in Hanawa to be etched other than such that its dimension is the same as the resist pattern overlying the antireflective coating. Ito et al. U.S. Pat. No. 5,547,787 (Aug. 20, 1996) for Exposure Mask, Exposure Mask Substrate, Method For Fabricating The Same, And Method For Forming Pattern Based On Exposure Mask, discloses an arrangement similar to that of the Hanawa '560 patent.
In order to achieve densely packed well spacing, Applicants developed a laser interferometric lithographic system for exposing selective portions of a layer of photoresistive material on a substrate. Applicants' system is described in the copending U.S. patent application Ser. No. 08/721,460 filed Sep. 27, 1996, entitled Laser Interferometric Lithographic System Providing Automatic Change Of Fringe Spacing, which is incorporated herein by reference. Instead of applying a physical mask over the photoresistive material to shield portions of it, the photoresistive material is exposed to the light interference pattern of a laser, i.e. a fringe pattern. The interference pattern exposes only selective portions of the photoresistive material. By making the interference pattern very tightly spaced (i.e. of fine pitch), the pattern of exposed portions of photoresistive material can also be very tightly spaced. Very densely packed well arrays may be formed from the tightly spaced pattern of exposed photoresistive material.
In order to make densely packed well arrays with a high degree of precision it is necessary to carry out the laser interference lithography on a very smooth, low reflection surface. This is particularly true when precise far submicron patterning is desired. The present invention may increase the precision of forming FED well arrays using a method of laser interference lithography by reducing the amount of laser light that is reflected off the FED substrate and onto the backside of the photoresistive material.
Applicants have determined that it may be beneficial to the formation of wells on a substrate to form a laser lithographic mask structure having multiple layers in a stack which undercut or overhang one another. In particular it has been discovered that a desirable well formation may be made using a mask structure having a lower layer (i e. adjacent the substrate) which is undercut below an overhanging upper layer.